The escalating requirements for increased densification and performance in ultra-large scale integration semiconductor wiring require integrated circuits capable of operating at higher speeds while having reduced-size geometries and greater packing densities. The shrinkage of geometries into the submicron range has increased circuit density, reduced contact holes, and narrowed line widths. Consequently, the resistance of the device elements increases along with the resistance capacitance (RC) time constants, thereby limiting the overall device speed. The rapid drive toward increased densification has strained the limits of existing materials and methodology, thereby requiring responsive changes in various aspects of semiconductor manufacturing technology.
Conventional practices employed in the manufacture of semiconductor devices, such as bulk silicon CMOS devices, confront various fundamental performance and reliability limitations, particularly in scaling down the size of a device. These limitations include high junction capacitance, ineffective isolation and latch-up sensitivity. High junction capacitance is primarily attributed to high doping levels required to prevent transistor punch-through and parasitic leakage or field turn on. Scale down LOCOS techniques reduces the effective spacings separating adjacent active regions in a semiconductor substrate and, thereby, increases transistor cross-talk and/or latch-up problems. In order to overcome these problems, conventional practices involve the use of larger than minimum isolation spacings and areas, which is inconsistent with the requirements for high densification. Other conventional approaches comprise the use of inefficient guard ring/bar structures which also increases the die size. An increase in die size requires longer interconnects and, hence, results in products with reduced integrated circuit speeds, i.e., greater RC delays.
A conventional alternative design to avoid the disadvantages of the LOCOS techniques, or modified LOCOS techniques, comprises trench isolation. Advantages of trench isolation include improved latch up and field turn on. However, trench isolation is attendant upon various problems, such as I-V kinks, sidewall leakages, low gate oxide breakdowns, and require significantly more complicated manufacturing steps. In order to overcome trench induced sidewall leakages, higher doping is normally introduced along trench sidewalls. Such high doping increases the junction capacitance. The disadvantageous unreliability and performance attributed to the gate oxide and junction capacitance, respectively, render trench isolation unsatisfactory for high volume production.
Another conventional approach is known as silicon-on-insulator (SOI) structures, wherein, a buried oxide region is provided under the surface semiconductor substrate in the active region. SOI structures advantageously provide lower junction capacitance, improved isolation and improved latch up. However, SOI structures suffer from various problems, such as a high number of defects, I-V kinks due to floating body effects and lattice heating, high source/drain resistance and random threshold voltage behavior.
Other attempts to satisfy the requirements for increased densification include use of refractory metals and refractory metal silicides which exhibit high conductivity and low resistance and form highly reliable interconnect patterns. However, it has become increasingly difficult to achieve the requisite planarized topography to satisfy the demands for multilevel semiconductor devices. Damascene techniques have been developed which basically comprise forming an opening in a dielectric layer and filling the opening with conductive material. See, for example, Mo, U.S. Pat. No. 4,764,484 and Smith et al., U.S. Pat. No. 5,055,423.
There exists a need for a semiconductor device having an improved isolation structure, particularly for ultra high density integrated circuitry. There also exists a need for a simplified, efficient, cost-effective method of manufacturing a semiconductor device with improved isolation, which method can be integrated into conventional MOSFET methodology. There further exists a need for a method which simplifies deep-submicron technology and, facilitates the definition of gate electrode dimensions yielding a semiconductor device exhibiting lower junction capacitance, higher performance, improved reliability and particularly improved topography.